To fill in this technology gap, NTT Microsystem Integration Laboratories is developing technology that uses the silicon technology cultivated with LSIs as a core technology for fabricating and converging ultrafine LSIs and MEMS devices on a silicon wafer while providing a seamless bridge to Jisso technologies. This seamless integration technology (SeaiT), as it is known, aims to achieve smooth convergence between the heterogeneous functions performed by microelectronics and micromachines [2], [3].
As shown in Fig. 3, seamless integration technology for converging LSI and MEMS is intended to fabricate microscopic MEMS devices and wiring with a size of 10 µm to 1 mm made of metal or silicon in a layered manner. This calls for fabrication technology that will produce little damage to the LSI. Specifically, it must be a low-temperature process and must not use dry etching, which could damage LSIs, for example. Accordingly, to form MEMS structures without incurring such damage, we are developing low-temperature plating techniques as well as 10-µm-level thick-film multilevel interconnection technology using photosensitive organic resins and other advanced materials.
As shown in Fig. 3, seamless integration technology for converging LSI and MEMS is intended to fabricate microscopic MEMS devices and wiring with a size of 10 µm to 1 mm made of metal or silicon in a layered manner. This calls for fabrication technology that will produce little damage to the LSI. Specifically, it must be a low-temperature process and must not use dry etching, which could damage LSIs, for example. Accordingly, to form MEMS structures without incurring such damage, we are developing low-temperature plating techniques as well as 10-µm-level thick-film multilevel interconnection technology using photosensitive organic resins and other advanced materials.
Concept of seamless integration technology.
Nanyoly Mendez
CAF
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